基于FPGA和单片机的多功能等精度频率计

范文编号:JD126  字数:9504,页数:38

摘   要
  
本文主要论述了利用FPGA进行测频计数，单片机实施控制实现多功能频率计的设计过程。该频率计利用等精度的设计方法，克服了基于传统测频原理的频率计的测量精度随被测信号频率的下降而降低的缺点。等精度的测量方法不但具有较高的测量精度，而且在整个测频区域内保持恒定的测试精度。该频率计利用FPGA来实现频率、周期、脉宽和占空比的测量计数。利用单片机完成整个测量电路的测试控制、数据处理和显示输出。
本文详细论述了硬件电路的组成和单片机的软件控制流程。其中硬件电路包括键输入模块、显示模块、输入信号整形模块以及单片机和FPGA主控模块。设计器件采用Atmel公司的单片机AT89C51和Altera公司的EPF10K20TC144-3。键输入模块设置5个功能键；显示模块用8只74LS164完成LED的串行显示；被测信号经限幅后由两级直接耦合放大器进行放大，再经施密特触发器整形后输入FPGA；标准频率采用50MHz。

关键词：频率计；测频；等精度；单片机；FPGA

Abstract
The reach paper mainly discussed the design process of multi-function cymometer that uses FPGA to count the frequency measurement and cymometer is also controlled by single chip computer. The cymometer makes use of equal-accuracy design that can overcome the disadvantage of traditional measuring principle, which precision declines as measured signal frequency does. The equal-accuracy measurement not only has higher measuring precision, but also can keep invariable measuring precision in whole area of frequency.
This cymometer uses FPGA to realize the measuring count of frequency、period、pulse width and occupy-empty ratio. Single chip computer completes the rest control、data processing and display output of the system.
This essay discusses the compose of hardware circuit and software control flow of single chip computer in detail. Hardware circuit includes key input module、display module、plastic module of input signal、single chip computer control module and FPGA main control module.
The cymometer adopts single chip computer AT89C51 of Atmel company and EPF10K20TC144-3 of Altera company. Key input module has 5 function key. Display module uses eight 74LS164 to realize the serial display of LED. First, the measuring signal amplitude is limited. Second, the signal is amplified by two class direct coupling amplifier. Finally, the signal inputs FPGA after it is trimmed by Smitter trigger. Standard frequency is 50MHz.

Key words:  Cymometer; Frequency measurement; Equal-precision; Single chip computer; FPGA

目    录
1  绪论........................................................................ 1
1.1研究背景及目的...............................................................1
1.2 频率计相关研究状况 .........................................................2
1.3 等精度数字频率计实现方法和器件选择 .........................................2
1.3.1  设计方法...............................................................  2
1.3.2  器件选择...............................................................  4

2  系统总体设计 ............................................................... 5
2.1 系统组成....................................................................5
2.2 等精度测频法误差分析 ...................................................... 6
2.3 基本性能指标............................................................... 7

3  硬件部分电路设计与实现 ......................................................8
3.1 CPLD/FPGA测量模块整体设计 ..................................................8
3.2 电路单元分模块设计..........................................................9
3.2.1  频率/周期测量模块 ...................................................... 9
3.2.2  脉冲宽度和占空比测量模块.................................................10
3.2.3  电源模块...............................................................  11
3.2.4  输入信号放大整形模块.....................................................12

4  软件部分设计...............................................................  13
4.1 单片机主体控制模块..........................................................13
4.2 各子模块流程图及汇编源程序..................................................18
4.2.1  测频子模块 ..............................................................18

4.2.2  显示子模块 ..............................................................21
4.2.3  键盘扫描子模块...........................................................23
4.2.4  其他相关子模块 ..........................................................28

结论........................................................................... 30
致谢 ...........................................................................31
参考文献 .......................................................................32
附录1...........................................................................33
附录2 ..........................................................................34

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