编号:JD1103 集成运放参数测试仪

范文编号:JD1103  范文字数:8375,页数:31

摘要：本系统参照片上系统的设计架构、采用FPGA与SPCE061A相结合的方法，以SPCE061A单片机为进程控制和任务调度核心；FPGA做为外围扩展，内部自建系统总线，地址译码采用全译码方式。FPGA内部建有DDS控制器，单片机通过系统总线向规定的存储单元中送入正弦表；然后DDS控制器以设定的频率，自动循环扫描，生成高精度，高稳定的5Hz基准测量信号。扫频信号通过对30MHz的FPGA系统时钟进行分频和外部锁相环（FPGA采用FLEX10K10无内部锁相环）倍频，产生高频率稳定度、幅值稳定度的扫频信号。放大器参数测量参照GB3442-82标准，低频信号幅度的测量采取AD高速采样，然后进行数字处理的方法；高频信号的幅度直接采用集成有效值转换芯片测得。A/D转换采用SPCE061A内部自带的10位AD。SPCE061A主要实现用户接口界面（键盘扫描、液晶显示、数据打印以及其他服务进程的调度）、AD转换以及测量参数（Vio Iio Kcmr Avd BWG Tr）计算、与上位机通信等方面的功能。上位机主要实现向下位机发送测量指令、与下位机交换测量数据、以及数据的存储、回放、统计。
 
关键词： 参数测量 运算放大器 DDS FPGA SPCE061A 数字信号处理
Abstract: In light of this system on-chip system design architecture, using a combination of FPGA and SPCE061A ways to SPCE061A SCM process control and task scheduling for the core; FPGA as an external expansion, internal self-built system bus, the address decoding all-Decoding. FPGA internal built DDS controller, microcontroller through the system bus to the provisions of the storage unit into the sine table; then DDS controller to set the frequency, auto-loop scanning, generating high-precision, high stability, 5Hz baseline measurement signal. Sweep the signal through the FPGA system clock 30MHz sub-band and the external phase-locked loop (FPGA using FLEX10K10 not have an internal phase-locked loop) frequency doubling, resulting in a high frequency stability, amplitude stability of the sweep signal. Amplifier parameter measurement reference GB3442-82 standard, low-frequency signal amplitude measurements taken by AD high-speed sampling, and then digital processing methods; high-frequency signals using an integrated RMS magnitude of the direct conversion chip measured. A / D converter uses the internal SPCE061A native 10-bit AD. Main achieved SPCE061A User Interface (Keyboard scanning, LCD display, data printing and other services to the process of scheduling), AD conversion, and measured parameters (Vio Iio Kcmr Avd BWG Tr) calculated with the host computer communication, etc. functions. Host machine is mainly send the measure to achieve the down-bit machine instructions, and the next crew exchange of measurement data, and data storage, playback, statistics.

Key words: parameter measurement op-amp DDS FPGA SPCE061A digital signal processing
目 录
第一章 方案比较设计与论证 5
1.1测量电路模块 5
1.1.1测试信号源部分 5
1.1.2主测试电路 5
1.1.3信号放大电路 6
1.1.4滤波电路 6
1.2信号采集模块 7
1.3用户接口模块 7
1.3.1 显示方案: 7
1.3.2 键盘输入方案: 7
第二章 整机工作原理与功能实现 8
第三章 各子模块的设计 12
第四章 理论计算及分析 18
第五章 电路图及有关设计文件 23
第六章 系统测试 27
参考文献： 30
第七章 结论 31

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