多功能频率计的设计

范文编号:JD221    字数:23273,页数:67       

摘    要
频率是电子技术领域内的一个基本参数，同时也是一个非常重要的参数稳定的时钟在高性能电子系统中有着举足轻重的作用，直接决定系统性能的优劣。随着电子技术的发展，测频系统使用时钟的提高,测频技术有了相当大的发展，但不管是何种测频方法，±1个计数误差始终是限制测频精度进一步提高的一个重要因素。
本设计阐述了各种数字测频方法的优缺点。通过分析±1个计数误差的来得出了一种新的测频方法：检测被测信号，时基信号的相位，当相位同步时开计数，相位再次同步时停止计数，通过相位同步来消除计数误差，然后再通过算得到实际频率的大小。根据M/T法的测频原理，已经出现了等精度的测频方法但是还存在±1的计数误差。因此，本文根据等精度测频原理中闸门时间只与测信号同步，而不与标准信号同步的缺点，通过分析已有等精度测频方法所存±1个计数误差的来源，采用了全同步的测频原理在FPGA器件上实现了全同步字频率计。根据全同步数字频率计的测频原理方框图，采用VHDL语言，成功编写出了设计程序，并在MAX+PLUSⅡ软件环境中，对编写的VHDL程序进了仿真，得到了很好的效果。最后，又讨论了全同步频率计的硬件设计并给出了电路原理图和PCB图。对构成全同步数字频率计的每一个模块，给出了较详细设计方法和完整的程序设计以及仿真结果。
关键词：FPGA、频率计、VHDL语言、MAX+PLUSⅡ
Abstract
Frequency is a basic parameter of electronics field,meanwhile,it’s a very important parameter.Stable clock is very important in high performance electronics system,determining the syetem performance directly.With the development of technology of electronics,the frequency measurement system using higher clock,the frequency measurement technology has very nice development.In despite of using all other advanced frequency measurement methods,the positive and negative 1 errors was a very important factor that stop frequency measurement precision improving all through.
The design expound the advantage and disadvantage of most digital frequency measurement methods.Through analyzing the origin of the positive and negative 1 errors,got a new frequency measurement methods:checking the measured and standard signal’s phase,if the phase is synchronous,then the counters start counting,when the signal’s phase is synchronous again,the counter stopping working,by phase in-phase to eliminate counting errors,then getting the real frequency through calculating.By this way’s guide,the design of complete digital cymometer was successfully completed with using VHDL(Very High Speed Integrated Circuit Hard Design Language）hardware description language and simulated it right.According to all of Synchronous Digital Block diagram of the frequency measurement using VHDL,the successful preparation of the design process,and in MAX+PLUS II software environment,the preparation of procedures for VHDL simulation,obtained very good results.Lastly,the frequency synchronization of the whole discussion of the hardware design and gives the circuit schematics and PCB plans.All of a synchronous digital frequency of each module,is a more detailed design and integrity of the process design and simulation results.
Keyword：FPGA、Cymometer、VHDL、MAXPLUSⅡ
目  录

第1章绪论................................................................. 1
1.1  课题背景 ..............................................................1
1.2  频率计概述.............................................................1
1.3  频率计发展现状 ........................................................2
1.4  FPGA概述.............................................................. 3
1.5  FPGA原理及结构.........................................................5
1.5.1  查找表（Look-Up-Table)的原理与结构...................................5
1.5.2  基于查找表（LUT)的FPGA的结构.........................................5
1.5.3  查找表结构的FPGA逻辑实现原理.........................................7
1.5.4  其他类型的FPGA和PLD .................................................7
1.6  VHDL简介 ..............................................................8
第2章全同步频率测量方法的研究 .............................................9
2.1  常用的数字频率测量方法.................................................9
2.1.1  直接测频法...........................................................9
2.1.2  多周期同步测频方法 .................................................10
2.2  提高频率测量精度的方案研究............................................12
2.2.1  采用对标频信号计数的修正来提高测量精度..............................12
2.2.2  相检式多周期同步测频法 .............................................13
2.3  全同步数字频率计的工作原理 ...........................................15
2.3.1  全同步频率测量的误差分析............................................15
2.3.2  全同步数字频率计原理框图 ...........................................16
第3章基于FPGA器件的功能模块电路设计...................................... 18
3.1  脉冲同步检测电路......................................................18
3.2  计数器............................................................... 19
3.3  锁存器............................................................... 20
3.4  乘法器............................................................... 20
3.5  除法器 ...............................................................28
3.6  控制器 ...............................................................34
3.7  译码电路..............................................................36
3.8  二十进制转换模块......................................................36
3.9  顶层VHDL程序设计及整体仿真结果........................................39
第4章 FPGA配置方案的设计...................................................41
4.1  EPF10K30ATI144-3 FPGA芯片简介........................................ 41
4.2  EPC2配置芯片简介......................................................41
4.3  配置模式............................................................. 41
4.4  下载方式..............................................................42
4.5  硬件电路原理图设计....................................................43
第5章 PCB系统板的设计 .....................................................45
结论及展望................................................................ 47
结论.............................................................. ........47
展望 ......................................................................47
参考文献.................................................................. 50
致谢 ......................................................................51
附录A：VHDL部分源程序 .....................................................52

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