字数:6352.页数:16
Abstract:The MC88920 Clock Driver utilizes phase–locked loop technologylock its low skew outputs’ frequency and phase onto an input referenceclock. It is designed to provide clock distribution for CISC microprocessoror single processor RISC systems. The RST_IN/RST_OUT(LOCK) pinsprovide a processor reset function designed specifically forMC68/EC/LC030/040 microprocessor family.The PLL allows the the high current, low skew outputs to lock ontosingle clock input and distribute it with essentially zero delay to multiplelocations on a board. The PLL also allows the MC88920 to multiply a
key words:low skew Driver PLL LOCK 目录
|
上一篇:基于MPC97H73的简介及电路设计 | 下一篇:基于MC12430的芯片简介及应用电路.. |
点击查看关于 MC88920芯片 简介 应用电路 设计 的相关范文题目 | 【返回顶部】 |