扩展扫描树结构优化中的一种低费用方法

范文字数:13545,页数:33  有开题报告，任务书

摘要
 随着超大规模集成技术的迅猛发展，集成电路的测试日益成为一个挑战。测试生成的时间复杂性非常高。全扫描设计是最重要的可测试性设计方法之一，在这个方法中，全部触发器都具有全可控性和全可观察性。在测试模式下，所有触发器在功能上形成一个或多个扫描链，各个扫描链通过扫描移位，所有触发器都可被设置成任意期望的逻辑值。尽管全扫描测试可以彻底地降低测试生成的复杂性，但测试应用时间太长，测试功耗过高，因此测试费用非常高，降低测试费用是数字电路测试中当务之急要解决的问题之一。
 扫描树技术被提出用来减少测试应用时间。在这些技术中，扫描单元被构造成一个树型结构。对比单扫描链型结构，电路中最长的扫描链的长度降低了，从而降低了测试数据量和测试应用时间。在扫描操作中，经过根扫描单元测试数据被扫描进入扫描树的每一个节点。扫描单元在扫描树的同一级上有相同的测试数据。因此，为了保持故障覆盖不变，同一级上的所有扫描单元对所有的测试向量相容。我们先前提出了一种扩展相容性扫描树结构，这种技术通过添加逻辑非和异或函数扩展了扫描单元的相容性，并对相容的扫描单元移入相同的测试向量值，大大降低了测试应用时间和平均测试功耗。但这种技术的测试硬件开销高，并且扫描输出个数多，给测试响应数据压缩带来了困难。
 本文提出了一种基于哑元的扩展相容性扫描树构造方法。此方法有效地降低了电路的扫描输出个数。从而降低了测试响应数据量，节省了许多数据压缩的硬件，并为测试效率的提高带来了潜在的好处。实验结果展示了我们的方法在保持改进的扩展相容性方法的优点的同时，扫描输出的个数比原始的扩展相容性方法有显著的降低，对于ISCAS’89的部分电路，扫描输出的个数最大降低了48.3%。
 关键字：可测性设计，全扫描测试，扫描树，低功耗测试

A Low Cost Test for Extended Compatibilities Scan Tree Architecture ABSTRACT
 With the transistor counts exponentially increasing, scan-based designs are widely employed to reduce test generation time. Full scan-based design is one of the most important designs for testability (DFT) methodologies in very large scale integration (VLSI) circuits and in system-on-chip (SoC) cores. In this DFT methodology, all flip-flops are enhanced to scan cells, and test application time depends on the length of the longest scan chain. Though full scan design reduces test generation complexity drastically, the test cost including test application time, test data volume and test power is very high, and it increases the cost of automatic test equipment (ATE).
 Recently, scan tree techniques have been proposed to reduce test application time. In these techniques, scan cells are constructed into a tree structure. The length of the longest scan chain is reduced. During scan operation, test data are shifted into the scan tree via one scan cell at the root. The scan cells in the same level have the same shifted test data. Therefore, to keep fault coverage, the scan cells should be compatible for all the test vectors. We previously proposed an extended compatibilities scan tree technique, employing logic NOT and XOR functions, reduces test application time and average test power drastically by shifting the same test values into(out from) the compatible scan flip-flops simultaneously. However, the hardware overhead is higher. In particular, the number of scan outputs is too larger so that the compact of test response data is difficult.
 This thesis proposes a scan tree architecture of extended compatibilities based on the concept of dumb element. This method can efficiently reduce the number of scan outputs. Experimental results show that our approach achieves almost the same test application time, test input data volume, test power and area overhead compared with the previous construction. For S38584 of ISCAS’89 benchmark circuits, the test response data volume reduces 48.3%.
 

 Keywords：design for testability, full scan testing, scan tree, low power testing

目录

摘要 I
ABSTRACT II
1绪论 1
1.1研究背景 1
1.2研究目标及其内容 3
1.2.1研究目标 3
1.2.2研究内容 4
1.3文章的组织 4
2.扫描树结构 5
2.1构造扫描树 5
3.扩展扫描树技术 7
3.1扩展相容性的概念 7
3.2构造扫描树 8
3.3减少扫描输出个数 9
3.4降低平均功耗 11
4扩展相容性扫描树的构造方法 12
4.1相容图 12
4.2原始扩展相容性扫描树构造算法 12
4.3改进的扫描树构造算法[28] 14
4.3.1扫描单元重新分组 15
4.3.2分组重新排序 16
4.3.3扫描树倒置 16
4.3.4扩展扫描树的改进算法 16
4.4此算法的缺点 17
5.基于哑元的扩展相容性扫描树构造方法 18
5.1子节点的表示 18
5.1.1异或节点为其子节点的唯一前驱节点 18
5.1.2异或节点为其子节点的两个前驱节点之一 18
5.2新的扫描树构造方法 19
6.平台工具选择及实验结果与结论 21
6.1平台工具选择 21
6.2实验结果 22
总结与展望 24
致谢 25
参考文献 26

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