基于DSP的数字存储示波器的显示及控制接口的FPGA设计

范文编号:ZD1043    范文字数:12071,页数:30

摘要

 普通DSP数字存储示波器的显示及控制接口主要是利用各种模拟电子器件或者是数字芯片整合而成，与用FPGA设计的显示及控制接口相比，前者的各种缺点比如价格昂贵、开发困难等都暴露了出来。由于FPGA的各种优点，比如操作灵活、开发迅速、投资风险低、可多次编程擦写和系统可编程等特点，其在今后的电子设计领域必将成为重点。所以用FPGA设计的显示及控制接口也是十分有必要的。
 基于DSP的数字存储示波器的显示及控制接口的FPGA设计的主要内容有三部分，一是串行输入并行输出的数据口，二是中断扩展接口，三是时钟分频器，用于调试。其中FPGA主要用Verilog HDL语言进行设计，芯片选用Actel公司的ProASIC3系列FPGA A3P030型。根据仿真波形结果，所有输出依据输入实时变化，完全达到了设计要求。
 
关键词：FPGA；数字存储示波器；显示控制接口

Abstract
 Traditionally，the display and control interface in digital shortage oscillograph is mainly made up of diversified analog electronic devices and digital electronic chips. Compared with he display and control interface in digital shortage oscillograph based on FPGA，the former have exposed many disadvantages such as costliness in price and difficulties in development. In view of the many advantages in FPGA, such as operating flexibility, rapid development ,the lower investment risk, and it is erasable and programming multiple-system programmable. It will probably become the focus in the field of electronic designing. Therefore, the display and control interface based on FPGA is also very necessary.
 The design of FPGA of Display and control interface in digital shortage oscillograph based on DSP mainly has three parts，first one is data interface which transfer serial data into parallel data，the second one is interrupt extend interface，and the third one is clock signal divider，which used in system debugging. In the process we design this FPGA，we used language of Verilog HDL，and the we chose Actel A3P030 FPGA in ProASIC3 family. Based on the final results of computer Simulation，all the outputs varies in the light of changes of input ，the design completely accord with requirement.
 
Keyword: FPGA; Digital shortage oscillograph; Display and control interface

目录

摘要 Ⅰ
Abstract Ⅱ
1绪论 1
1.1背景介绍 1
1.2显示控制接口方案介绍 4
1.3硬件、设计仿真平台介绍 5
2模块设计 9
2.1显示接口模块 9
 2.1.1显示接口模块方案设计 9
 2.1.2 显示接口模块仿真 12
 2.2中断扩展模块 14
 2.2.1中断扩展模块方案设计 14
2.2.2中断扩展模块仿真 14
2.3 时钟分频模块 18
3.2.1 时钟分频模块方案设计 18
3.2.2 时钟分频模块仿真 18
3总结与展望 20
3.1 总结 20
3.2 展望 20
致谢 21
参考文献 22
附录 23
附录一:原理图 23
附录二:Verilog 程序 24

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